The so called PUFs (Physically Unclonable Functions) are used to generate a secret key from physical properties of a chip, which randomly differ from chip to chip. This secret key is not stored on the chip (e.g. in an NVM), but is re-generated (at least) every time the chip is powered up. So a reverse engineering of the structure or memory content of a chip cannot reveal this key, since it is not existing in the un-powered chip. The realization of a PUF can be based on specially designed hardware, or can make use of the properties of anyway existing circuitry, that is randomly varying between chips. The main problem for the realization of a PUF lays in the error probability for the bits, when a key is re-generated under different conditions (different temperature, voltage, . . . ). The higher the error probability, the higher the effort for the correct recovery of the key becomes. Above a certain error probability no key recovery is possible. Various methods to handle the error probability during key recovery are known from other PUF implementations and are not part of this discussion.
Some conventional solutions employ specifically designed and implemented PUF hardware which typically make it possible to achieve low bit error probabilities. Accordingly, a relatively small effort for a downstream error correction is required. However, such dedicated PUF hardware needs to be specially implemented on a chip and thus needs extra area. The PUF hardware also needs to be implemented on every chip of a series, even if only a few chips need a physically unclonable function. For the chips that do not need a PUF, this results in wasted area.
Hence, it is desired to provide a concept which reduces the amount of specially designed and implemented PUF and/or allow the use of general purpose hardware on a chip for generating a PUF response.